Generally, the industry of semiconductor manufacturing involves highly complex techniques for fabricating integrated circuits using semiconductor materials which are layered and patterned onto a substrate, such as silicon. An integrated circuit is typically fabricated from a plurality of reticles or masks. Initially, circuit designers provide circuit pattern data, which describes a particular integrated circuit (IC) design, to a reticle production system, which transforms the pattern data into a plurality of reticles. One emerging type of reticle is an extreme ultraviolet (EUV) reticle that is comprised of a plurality of mostly reflecting layers and a patterned absorber layer. A set of reticles are generally used in multiple photolithography processes to transfer the reticle pattern to multiple layers in a semiconductor wafer to thereby form a plurality of integrated circuit (IC) dice.
Due to the large scale of circuit integration and the decreasing size of semiconductor devices, the reticles and fabricated devices have become increasingly sensitive to defects. These defects, if uncorrected, can cause the final device to fail to meet the desired performance due to electrical timing errors. Even worse, such defects can cause the final device to malfunction and adversely affect yield.
As the photolithography used in IC manufacturing is migrating from 193 nm to extreme ultraviolet (EUV), the shrinking size in photomask features and defects of interest continues to push the performance limit of the imaging-based deep ultraviolet (DUV) optical inspection tool. Furthermore, tool-tool matching has also become more difficult as a result of the higher imaging sensitivity to aberration due to the nature of the EUV photomask. There is a strong demand for tighter control of the optical aberration. The utilization of linear polarization in addition to the circular polarization in EUV mask inspection has made this task particularly challenging due to the intrinsic limit of current lens coating design.